1. Field
The following description relates to a semiconductor design technology, and more particularly, to the charge pump circuit of a semiconductor device.
2. Description of Related Art
In order to drive a liquid crystal, a display driver integrated circuit (DDI), such as a Liquid Crystal Display/Active-matrix Organic Light-emitting Diode (LCD/AMOLED) Driver integrated circuit (IC), for a general mobile apparatus includes a circuit generating source line driving voltage, a circuit generating common electrode driving voltage, a circuit generating gamma driving reference voltage, and a circuit generating liquid crystal on/off voltage.
In addition, a DDI includes a charge pump circuit for providing the circuits with power voltage. The charge pump circuit receives external battery power voltage of approximately 2.5 volts to 3.3 volts, boosts the received voltage to generate boost voltage in a range of 4.5 volts to 6 volts, and provides the circuits with the boost voltage as power voltage (AVDD).
FIG. 1A is a block diagram illustrating an example of an operation mechanism of a related charge pump circuit.
Referring to FIG. 1A, a general charge pump circuit includes a charge pump operation control unit 10 that generates control signals (SW1, SW3, SW2, SW4) for controlling the operation of a charge pump 30 using a reference clock, a level shifter 20 that adjusts a voltage level of the control signals (SW1, SW3, SW2, SW4) generated by the charge pump operation control unit 10 to be consistent with a level of the power voltage (AVDD) provided to the transistors formed on the charge pump 30, and the charge pump 30 that performs a charge-pumping operation in response to the control signals (SW1, SW3, SW2, SW4) output from the level shifter 20.
For reference, the charge pump operation control unit 10 and the level shifter 20 may be categorized together as a pumping control unit 40.
FIG. 1B is a circuit diagram illustrating an example of the related charge pump 30 in detail.
Referring to FIG. 1B, the charge pump 30 performs the operation of charge-pumping power voltage (AVDD) two times (AVDD*2 (VGH)).
Specifically, the charge pump 30 includes a first switch (M11) having an end that is connected to power voltage (AVDD) to control on/off in response to the first control signal (SW1), a first capacitor (C11: pumping cap) having one end that is connected to an other end of the first switch (M11), a second switch (M13) having one end that is connected to power voltage (AVDD) and an other end that is connected to the other end of the first capacitor (C11: pumping cap) to control on/off in response to the second control signal (SW3), a third switch (M12) having one end that is connected to the one end of the first capacitor (C11: pumping cap) and an other end that is connected to pumping voltage (AVDD*2 (VGH)) to control on/off in response to the third control signal (SW2), a second capacitor (C12: storaging cap) having one end that is connected to pumping voltage (AVDD*2 (VGH)) and an other end that is connected to ground voltage (VSS), and a fourth switch (M14) having one end that is connected to the other end of the first capacitor (C11: pumping cap) and an other end that is connected to ground voltage (VSS) to control on/off in response to the fourth control signal (SW4).
FIG. 1C is a timing diagram illustrating examples of control signals for controlling the operation of the related charge pump illustrated in FIG. 1B.
Referring to FIG. 1C, reference frequencies of the first to the fourth control signals (SW1, SW3, SW2, SW4, respectively) are the same. A pre-charge period is performed as the second and the third control signals (SW3, SW2, respectively) are inactivated while the first and the fourth control signals (SW1, SW4) are activated. A pumping period is performed as the second and the third control signals (SW3, SW2, respectively) are activated while the first and the fourth control signals (SW1, SW4) are inactivated.
In addition, levels of the control signals change at predetermined time intervals so that the first and the fourth control signals (SW1, SW4) and the second and the third signals (SW3, SW2, respectively) do not overlap with each other.
Furthermore, a pumping operation is performed as the pre-charge period and the pumping period are performed alternately.
For example, the first to the third switches (M11, M13, and M12, respectively) are PMOS transistors and, thus, the first to the third control signals (SW1, SW3, SW2, respectively) are inactivated during the period of logic ‘high’ and activated during the period of logic ‘low’. On the contrary, the fourth switch (M14) is an NMOS transistor and, thus, the fourth control signal (SW4) is activated during the period of logic ‘high’ and inactivated during the period of logic ‘low’.
FIG. 1D is a detailed circuit diagram illustrating an example of an operation of the related charge pump illustrated in FIG. 1B according to the timing of the control signals illustrated in FIG. 1C.
Referring to FIG. 1D, in a pre-charge period, the first and the fourth control signals (SW1, SW4) are activated and, thus, the first and the fourth switches (M11, M14) are closed. The second and the third control signals (SW3, SW2, respectively) are inactivated and, thus, the second and the third switches (M13, M12, respectively) are opened. As a result, electric charge corresponding to power voltage (AVDD) is pre-charged to the first capacitor (C11: pumping cap).
In addition, in a pumping period, the first and the fourth control signals (SW1, SW4) are inactivated and, thus, the first and the fourth switches (M11, M14) are opened. Further, the second and the third controls signals (SW3, SW2, respectively) are activated and, thus, the second and the third switches (M13, M12, respectively) are closed. As a result, electric charge pre-charged to the first capacitor (C11: pumping cap) is discharged and moves to the second capacitor (C12: storaging cap).
Accordingly, electric charge corresponding to power voltage (AVDD) charged in the second capacitor (C12: storaging cap) and voltage corresponding to power voltage (AVDD) of a C11M node are combined in the pumping voltage (AVDD*2 (VGH)). Thus, the pumping voltage (AVDD*2 (VGH)) has a voltage level (2*AVDD) two times as much as the power voltage (AVDD).
Meanwhile, in a related pumping circuit, a frequency of a reference clock and a pumping driving power is fixed to a specific value. Thus, electric current is wasted when a pumping operation is performed regardless of an operation period of a semiconductor device.
That is, the frequency of a reference clock and the pumping driving power of the above-described example of a pumping circuit are designed to generate enough pumping voltage to prevent a shortage of voltage when a semiconductor device consumes a considerable amount of pumping voltage in a relatively short period of time as the semiconductor device enters into an operation period with significant amount of external load.
Accordingly, a charge-pumping circuit according to the above-described example is bound to consume an excessive amount of electric current unnecessarily when a semiconductor device enters into an operation period with small amount of external load and, thus, does not require a considerable amount of pumping voltage in a relatively short period of time.
Therefore, in the case of pumping voltage generated through a charge-pumping circuit according to the above-referenced example, a voltage level changes significantly, which, as a result, causes an operation of a semiconductor device to be unstable.